1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same and more particularly, to a semiconductor device with the dual damascene structure in which the wire-to-wire capacitance is reduced and the propagation delay of signals is suppressed, and a method of fabricating the device without using any complicated process steps.
2. Description of the Prior Art
In recent years, there has been the increasing need to raise the speed of signal processing in semiconductor devices, especially in Large-Scale Integrated circuits (LSIs). The signal processing speed in LSIs is mainly dependent upon the operation speed of individual transistors and the delay of signals propagating through wiring lines.
Conventionally, the operation speed of transistors has been gradually raised according to their consecutive dimensional reduction. However, in LSIs fabricated under the design rule of 0.18 xcexcm or less, it has been found that the signal processing speed is affected more by the propagation delay of signals in wiring lines than by the operation speed of transistors.
To reduce the propagation delay of signals, vigorous development has been made to intend the use of copper (Cu) instead of aluminum (Al), because Cu is lower in electric resistance than Al. Since Cu is lower in vapor pressure than that of halides, it is difficult to be processed or patterned by ordinary dry etching processes at low temperatures. Thus, it is usual that wiring recesses are formed in a silicon dioxide (SiO2) layer and then, Cu is deposited on the SiO2 layer to fill the recesses with Cu, thereby forming wiring lines made of Cu in the recess. These Cu wiring lines constitute a Cu wiring layer.
The wiring structure thus formed is termed the xe2x80x9cdamascene structurexe2x80x9d. If the Cu wiring lines are simply formed in the recesses, the process is termed the xe2x80x9csingle damascene processxe2x80x9d. If the Cu wiring lines are formed in the recesses and at the same time, via holes for interconnecting the Cu wiring layer with an underlying wiring layer or underlying electronic elements are formed, the process is termed the xe2x80x9cdual damascene processxe2x80x9d. Considering the fabrication cost of LSIs, the dual damascene process is preferred to the single one.
FIGS. 1A to 1D show an example of the prior-art methods of fabricating an LSI using the dual damascene process.
First, as shown in FIG. 1A, a SiO2 layer 302 is formed on the surface of a single-crystal silicon substrate 301 as a first interlayer dielectric layer. Although the substrate 301 has specific electronic elements such as transistors and at least one wiring layer connected thereto, only a diffusion region 301a of one of the elements is illustrated in FIG. 1A for the sake of simplification.
A silicon nitride (SiNx) layer 303 is then formed on the SiO2 layer 302 serving as the first interlayer dielectric layer. The SiNx layer 303 serves as a second interlayer dielectric layer. The SiNx layer 303 is patterned by using a patterned photoresist film (not shown) to form an opening 303a exposing the surface of the underlying SiO2 layer 302. The opening 303a is located to overlap with the underlying diffusion region 301a of the substrate 301. The opening 303a forms an upper part of a desired via hole to be formed in the subsequent process steps.
Although any other openings are formed in the layer 303, only one of them is shown here for simplicity. The state at this stage is shown in FIG. 1A.
Subsequently, as shown in FIG. 1B, a SiO2 layer 304 is formed on the SiNx layer 303 to cover the whole substrate 1 as a third interlayer dielectric layer. The opening 303a is filled with the layer 303. Then, a patterned photoresist film 305 is formed on the SiO2 layer 304. The photoresist film 305 has a pattern corresponding to that of a desired wiring layer. Only a window 305a or the film 305 is shown in FIG. 1B for simplicity.
Using the patterned photoresist film 305 as a mask, the SiO2 layer 304 is selectively etched by an ordinary dry etching process to form a wiring recess 311 in the layer 304, as shown in FIG. 1C. The recess 311 extends on the SiNx layer 303 from back to forth in a direction perpendicular to the paper. During the same etching process, the underlying SiO2 layer 302 is selectively etched while the SiNx layer 303 with the opening 303a is used as a mask, thereby forming an opening 302a in the layer 302. The openings 302a and 303a, which are overlapped with each other and communicate therewith, constitute a via hole 312 interconnecting the recess 311 with the diffusion region 301a of the substrate 301. Thereafter, the photoresist film 305 is removed. The state at this stage is shown in FIG. 1C.
During the above-described etching process, the SiNx layer 303 serves as an etch stop layer for the SiO2 layer 302 and a masking layer therefor. Therefore, the SiO2 layer 302 can be selectively etched as explained above, resulting in the dual damascene structure, as shown in FIG. 1C.
A barrier layer 306, which is made of a metal such as tantalum (Ta) and titanium nitride (TiN), is formed to cover the exposed surfaces of the recess 311 and the via hole 312 and the diffusion region 301a, as shown in FIG. 1D.
A Cu plug 307 is then formed on the barrier layer 306 in the via hole 312, and a Cu wiring layer 308 is formed on the barrier layer 306 in the recess 311 so as to be contacted with the plug 307, as shown in FIG. 1D. The Cu plug 307 and the CU wiring layer 308 are formed by depositing a Cu layer to cover the entire SiO2 layer 304 using a plating, sputtering, or Chemical Vapor Deposition (CVD) process, and by selectively removing the Cu layer thus deposited by a Chemical Mechanical Polishing (CMP) process.
Finally, a SiNx layer 309 is formed on the SiO2 layer 304 to cover the Cu wiring layer 308. The layer 309 serves as a fourth interlayer dielectric layer and a diffusion prevention layer of Cu existing in the wiring layer 308.
However, the prior-art method shown in FIGS. 1A to 1D has the following problem.
Since the SiNx layer 303, which has a relative dielectric constant as high as approximately 7 to 8, is used as an etch stop layer during the etching process of the SiO2 layers 304 and 302, the wire-to-wire capacitance becomes extremely higher than the ease where the SiNx layer 303 is replaced with a SiO2 layer due to the fringing field effect. This increases largely the propagation delay of signals.
The same problem as above will occur if the SiNx layer 303 is replaced with a silicon oxynitride (SiON) layer having a relative dielectric constant of approximately 5 to 6.
To solve the above-described problem, improved methods have been developed, in which an organic dielectric layer is used as an interlayer dielectric layer rather than a SiNx layer. The organic dielectric layer is made of, for example, a polytetrafluoroethylene (PTFE), a fluorinated polyallyl ether, or a fluorinated polyimide. These improved methods are disclosed in the Japanese Non-Examined Patent Publication Nos. 10-112503 published in April 1998 and 10-150105 published in June 1998.
With the improved methods using the above-described organic dielectric layer, the above-described problem that the propagation delay of signals is increased can be solved, because the organic dielectric layers are considerably lower in relative dielectric constant than SiO2. However, these methods have other problems explained below.
Since the organic dielectric layers disclosed in the Japanese Non-Examined Patent Publication Non. 10-112503 and 10-150105 have a low heat- and plasma-resistant property, they tend to be changed in quality in the fabrication process sequence of LSIs (especially, in the dry etching process), resulting in increase of the relative dielectric constant. In other words, low relative dielectric constants of these layers are difficult to be realized as desired. Consequently, they cause a problem that the propagation delay of signals cannot be suppressed effectively.
Moreover, the organic dielectric layers necessitate complicated process steps of removing resist films used for patterning the same organic dielectric layers. This means that they cause another problem that the fabrication cost of LSIs becomes higher.
Accordingly, an object of the present invention is to provide a semiconductor device equipped with the dual damascene structure that suppresses the propagation delay of signals effectively, and a method of fabricating the device.
Another object of the present invention is to provide a semiconductor device equipped with the dual damascene structure that is fabricated without using any complicated processes, and a method of fabricating the device.
Still another object of the present invention is to provide a semiconductor device equipped with the dual damascene structure that prevents the fabrication cost increase, and a method of fabricating the device.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
According to a first aspect of the present invention, a semiconductor device equipped faith the dual damascene structure is provided, which is comprised of (i) a semiconductor substrate having a lower wiring layer and electronic elements; (ii) a first interlayer dielectric layer formed on the substrate; (iii) a second interlayer dielectric layer formed on the first interlayer dielectric layer, the second interlayer dielectric layer being made of a carbon-containing SiO2; (iv) a third interlayer dielectric layer formed on the second interlayer dielectric layer; (v) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer, the fourth interlayer dielectric layer being made of a carbon-containing SiO2; (vi) the first and second interlayer dielectric layers having a via hole penetrating therethrough, the via hole exposing the substrate; (vii) the third interlayer dielectric layer having a recess overlapping with the via hole, the recess being formed to communicate with the via hole; (viii) a metal plug formed in the via hole to be contacted with the lower wiring layer or the electronic elements in the substrate; (ix) a metal wiring layer formed in the recess; and (x) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer to cover the metal wiring layer.
With the semiconductor device according to the first aspect of the present invention, each of the second and forth interlayer dielectric layers is made of carbon-containing SiO2 that is lower in relative dielectric constant than SiNx. Therefore, the wire-to-wire capacitance is reduced compared with the case where a SiNx layer is used instead of the carbon-containing SiO2 layer. Thus, the propagation delay of signals can be suppressed effectively.
Also, the use of the carbon-containing SiO2 layers does not make the fabrication process steps complicated and therefore, the dual damascene structure can be fabricated without using any complicated processes and the fabrication cost increase can be prevented.
According to a second aspect of the present invention, a method of fabricating the semiconductor device according to the first aspect of the present invention is provided, which is comprised of the following steps of (a) to (i).
In the step (a), a semiconductor substrate having a lower wiring layer and electronic elements is prepared.
In the step (b), a first interlayer dielectric layer is formed on the substrate.
In the step (c), a second interlayer dielectric layer is formed on the first interlayer dielectric layer. The second interlayer dielectric layer is made of a carbon-containing SiO2.
In the step (d), an opening is formed in the second interlayer dielectric layer to overlap with the lower wiring layer or the electronic elements.
In the step (e), a third interlayer dielectric layer is formed on the second interlayer dielectric layer having the opening.
In the step (f), a patterned mask layer having a window is formed on the third interlayer dielectric layer. The window is located to overlap with the opening of the second interlayer dielectric layer.
In the step (g), the third interlayer dielectric layer is patterned to form a wiring recess in the third interlayer dielectric layer using the patterned mask layer while the first interlayer dielectric layer is patterned to form a via hole in the first interlayer dielectric layer using the second interlayer dielectric layer. The via hole communicates with the wiring recess.
In the step (h), a conductive layer is selectively formed to fill the wiring recess and the via hole after removing the patterned mask layer, thereby forming a wiring layer in the recess and a conductive plug in the hole. The wiring layer is contacted with the conductive plug.
In the step (i), a fourth interlayer dielectric layer is formed on the third interlayer dielectric layer to cover the wiring layer. The fourth interlayer dielectric layer is made of a carbon-containing SiO2.
With the method according to the second aspect of the present invention, the second interlayer dielectric layer, which is made of carbon-containing SiO2 that is lower in relative dielectric constant than SiNx, is formed on the first interlayer dielectric layer in the step (c).
Also, in the step (g), the third interlayer dielectric layer is patterned to form the wiring recess in the third interlayer dielectric layer using the patterned mask layer while the first interlayer dielectric layer is patterned to form the via hole communicating with the recess in the first interlayer dielectric layer using the second interlayer dielectric layer.
In the step (h), the wiring layer is formed in the recess and the conductive plug contacting with the wiring layer is formed in the hole. Furthermore, the forth interlayer dielectric layer, which is made of carbon-containing SiO2, is formed on the third interlayer dielectric layer in the step (i).
Therefore, the semiconductor device according to the first aspect of the present invention is fabricated.
According to a third aspect of the present invention, another method of fabricating the semiconductor device according to the first aspect of the present invention is provided, which is comprised of the following steps (axe2x80x2) to (ixe2x80x2).
In the step (axe2x80x2), a semiconductor substrate having a lower wiring layer and electronic elements is prepared.
In the step (bxe2x80x2), a first interlayer dielectric layer is formed on the substrate.
In the step (cxe2x80x2), a second interlayer dielectric layer is formed on the first interlayer dielectric layer. The second interlayer dielectric layer is made of a carbon-containing SiO2.
In the step (dxe2x80x2), a third interlayer dielectric layer is formed on the second interlayer dielectric layer.
In the step (exe2x80x2), the third interlayer dielectric layer is patterned to form a wiring recess therein to overlap with the lower wiring layer or the electronic elements.
In the step (fxe2x80x2), a patterned mask layer having a window is formed on the third interlayer dielectric layer. The window is located to overlap with the wiring recess of the third interlayer dielectric layer.
In the step (gxe2x80x2), the first and second interlayer dielectric layers are patterned to form a via hole penetrating the first and second interlayer dielectric layers using the patterned mask layer. The via hole communicates with the wiring recess.
In the step (hxe2x80x2), a conductive layer is selectively formed to fill the wiring recess and the via hole after removing the patterned mask layer, thereby forming a wiring layer in the recess and a conductive plug in the hole. The wiring layer is contacted with the conductive plug.
In the step (ixe2x80x2), a fourth interlayer dielectric layer is formed on the third interlayer dielectric layer to cover the wiring layer. The fourth interlayer dielectric layer is made of a carbon-containing SiO2.
With the method according to the third aspect of the present invention, in the step (exe2x80x2) of patterning the third interlayer dielectric layer, the underlying second interlayer dielectric layer made of a carbon-containing SiO2 serves as an etch stop layer. Therefore, the wiring recess can be formed in the third interlayer dielectric layer as desired.
Also, since each of the second and fourth interlayer dielectric layers is made of a carbon-containing SiO2, the semiconductor device according to the first aspect of the present invention is fabricated.
In a preferred embodiment of the present invention, the carbon-containing SiO2 contains a hydrocarbon (CH) group, and each of the second and fourth interlayer dielectric layers has a relative dielectric constant of approximately 5 or lower. If the relative dielectric constant is greater than approximately 5, the possibility that the wire-to-wire capacitance is unable to be suppressed becomes high.
In another preferred embodiment of the present invention, the carbon-containing SiO2 contains a Sixe2x80x94H group. The carbon-containing SiO2 has Sixe2x80x94C bonds. In addition to the Sixe2x80x94C bonds, it may contain Sixe2x80x94H groups or bonds. In this case, there are the same advantages as described above. The containing of Sixe2x80x94H groups produces an additional advantage that the relative dielectric constant becomes lower (the plasma-resistance property may degrade).
In still another preferred embodiment of the present invention, each of the first and third interlayer dielectric layers is made of a substance selected from the group consisting of plasma-deposited SiO2, fluorinated, plasma deposited SiO2 (SiOF), and hydrogen silisesquioxnane (HSQ). In this embodiment, the advantages of the invention can be exhibited conspicuously.